coreboot on PC Engines Alix 2c3

IMG_2883.JPG
I’ve been following coreboot (formally LinuxBIOS) for quite a while but my last attempt to run it ended disastrously a couple of years back on the defunct coreboot 3 branch, requiring an RMA for a new Alix 2c3 board & the purchase of additional tools.
A ThinkPad X60s was offered up by my friendly local “old computer” pusher which I chose to try coreboot on but before I bricked that, I thought I’d try the Alix again as I was in possession of the everything needed to debug or recover the board if things went wrong.
A lot of time was wasted trying to get things built on OS X & diverged into briefly trying CentOS 7 (systemd, run away) before settling on Debian 7.6 to build on.

Running apt-get install gcc make libncurses-dev doxygen iasl gdb flex bison will install the necessary dependencies to build coreboot on Debian following the build guide.

Selecting a board from the menu should set the ROM size as well but I was advised to double check, on the Alix 2c3 the flash chip is located under the board, my board had a AMIC A49LF040ATY-33F.
IMG_2891

Once the image was built, coreboot.rom was copied to the Alix running FreeBSD/i386 10-RELEASE & flashed with sysutils/flashrom built from ports.
Flashrom currently assumes that there’s a device node named /dev/cpu0 and sysutils/devcpu-data offers the necessary device but on FreeBSD it’s named /dev/cpuctl0, a symlink allows you to work around the hardcoded assumption once the micro_code service has been started.

service micro_code onestart
ln -s /dev/cpuctl0 /dev/cpu0

coreboot can then be programmed with flashrom -p internal:laptop=this_is_not_a_laptop -w ~/coreboot.rom

flashrom v0.9.7-r1711 on FreeBSD 10.0-RELEASE-p7 (i386)
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop… delay loop is unreliable, trying to continue OK.
========================================================================
WARNING! You may be running flashrom on an unsupported laptop. We could
not detect this for sure because your vendor has not setup the SMBIOS
tables correctly. You can enforce execution by adding
‘-p internal:laptop=this_is_not_a_laptop’ to the command line, but
please read the following warning if you are not sure.

Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See the manpage and http://www.flashrom.org/Laptops for details.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Proceeding anyway because user forced us to.
Found chipset “AMD CS5536”. Enabling flash write… OK.
Warning: unexpected second chipset match: “AMD CS5536”
ignoring, please report lspci and board URL to flashrom@flashrom.org
with ‘CHIPSET: your board name’ in the subject line.
Found AMIC flash chip “A49LF040A” (512 kB, LPC) at physical address 0xfff80000.
Reading old flash chip contents… done.
Erasing and writing flash chip… Erase/write done.
Verifying flash… VERIFIED.

Power cycling the box will result in text output or garbage depending on if your console speed settings have changed or not, coreboot defaults to the speed of 115200bps, the factory default speed of Alix is 38400bps & the default console speed of FreeBSD is 9600bps.

When attempting to generate a new image with different settings be sure to make clean before starting.
In my image I removed the “PS/2 keyboard init” option from the “Generic Drivers” menu. Still todo is building an image with PXE support, test booting other BSD’s, try different payloads, in particular Open Firmware & generate status data for submission to change board support status on wiki.

IMG_2886.JPG

Through the previously failed attempt to run coreboot 3 I ended up with a LPC.1a & a POST.5a mini-pci board, the LPC.1a is absolutely essential for testing if you do not have more advanced equipment which would allow you to re-program the flash chip. The LPC.1a is a secondary BIOS chip which can override the onboard the flash, allowing you to boot the system & reprogram the onboard chip again. J2 jumper allows you to select which chip to boot from. When reflashing the chip on the motherboard with flashrom with the LPC.1a inserted (and set to read only), flashrom trashed the image on the onboard chip. Rebooting the system & carefully removing the LPC.1a before re-flashing allowed the process to complete successfully.